View IRS2135DJPBF_9108824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.irf.com 1 3-phase bridge driver product summary description packages the irs213(3, 5)d are high voltage, high speed power mosfet and igbt drivers with three independent high and low side referenced output channels for 3-phase applications. proprietary hvic technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 2.5 v logic. an independent operational amplifier provides analog feedback of bridge current via an external current sense resistor. a current trip function which terminates all six outputs can also derived from this resistor. a shutdown f unction is available to terminate all six outputs. an open drain fault signal is provided to indicate that an over-current or undervoltage shutdown has occurred. fault conditions are cleared with the flt-clr lead. the output drivers feature a hi gh pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequencies appl ications. the floating channels can be used to drive n-channel power mosfets or igbts in the high side configuration which operates up to 600 v. absolute maximum ratings absolute maximum ratings features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transi ent voltage, dv/dt immune ? gate drive supply range from 10 v /12 v to 20 v dc and up to 25 v for transient ? undervoltage lockout for all channels ? over-current shutdown turns off all six drivers ? three independent half-bridge drivers ? matched propagation delay for all channels ? 2.5 v logic compatible ? outputs out of phase with inputs ? all parts are lead-free ? integrated bootstrap diode function irs2133d/irs2135d ( j&s ) pbf preliminary data sheet no. pd60264 rev a v offset 600 v max. i o +/- (min.) 200 ma / 420 ma v out 10 v C 20 v or 12 C 20 v t on/off (typ.) 500 ns deadtime (typ.) 230 ns 28-lead soic 28-lead pdip 44-lead plcc w/o 12 leads typical connection applications: *motor control *air conditioners/ washing machines *general purpose inverters *micro/mini inverter drives downloaded from: http:///
www.irf.com 2 irs2133d/irs2135d(j&s)pbf absolute maximum rati ngs indicate sustained limits beyond which dam age to the device may occur. all voltage parameters are absolute voltages refere nced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. zener clamps are included between v cc & com (25 v), v cc & v ss (20v), and v bx & v sx (20 v). recommended operating conditions the input/output logic timing diagram is shown in fig. 1. fo r proper operation the device should be used within the recommended conditions. all voltage parameters ar e absolute voltage referenced to com. the v s offset rating is tested with all supplies biased at a 15 v differential. note 1: logic operational for v s of (com - 8 v) to (com + 600 v). logic state held for v s of (com - 8 v) to (com C v bs ) . (please refer to the design tip dt97-3 for more details). note 2: the cao pin and all input pins (except ca+ & ca-) are internally clamped with a 5.2 v zener diode. symbol definition min. max. units v b1,2,3 high side floating supply voltage -0.3 625 v s1,2,3 high side floating offset voltage v b1,2,3 - 20 v b1,2,3 + 0.3 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc fixed supply voltage -0.3 25 v ss logic ground v cc - 20 v cc + 0.3 v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in logic input voltage (hin, lin itrip, sd & flt-clr) v ss -0.3 v cc + 0.3 v in,amp op amp input voltage (ca+ & ca-) v ss -0.3 v cc +0.3 v out,amp op amp output voltage (cao) v ss -0.3 v cc +0.3 v flt fault output voltage v ss -0.3 v cc +0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns (28 lead pdip) 1.5 (28 lead soic) 1.6 p d package power dissipation @ t a +25 c (44 lead plcc) 2.0 w (28 lead pdip) 83 (28 lead soic) 78 r th,ja thermal resistance, junction to ambient (44 lead plcc) 63 c/w t j junction temperature 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 c symbol definition min. max. units v b1,2,3 high side floating supply voltage v s1,2,3 +10/12 v s1,2,3 +20 v s1,2,3 high side floating offset voltage note 1 600 v ho1,2,3 high side floating output voltage v s1,2,3 v b1,2,3 v cc fixed supply voltage 10 or 12 20 v ss low side driver return -5 5 v lo1,2,3 low side output voltage 0 v cc v in logic input voltage (hin, lin itrip, sd & flt-clr) v ss v ss + 5 v in,amp op amp input voltage (ca+ & ca-) v ss v ss + 5 v out,amp op amp output voltage (cao) v ss v ss + 5 v flt fault output voltage v ss v cc v prelim i nary downloaded from: http:///
www.irf.com 3 irs2133d/irs2135d(j&s)pbf static electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, unless otherwise specified and t a = 25 c. all static parameters other than i o and v o are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the respec tive output leads: ho1,2,3 or lo1,2,3 . symbol definition min. typ. max. units test conditions v ih logic 0 input voltage (out = lo) 2.2 v il logic 1 input voltage (out = hi) 0.8 v fclr,ih logic 0 fault clear input voltage 2.2 v fclr,il logic 1 fault clear input voltage 0.8 v sd,th+ sd input positive going threshold 1.6 1.9 2.2 v sd,th- sd input negative going threshold 1.4 1.7 2.0 v v it,th+ itrip input positive going threshold 470 570 670 v it,th- itrip input negative going threshold 360 460 560 mv v oh high level output voltage, v bias - v o 1 v v in = 0 v, i o = 20 ma v ol low level output voltage, v o 400 mv v in = 5 v, i o = 20 ma i lk offset supply leakage curr ent irs213(3,5)d 50 v b1,2,3 = v s1,2,3 = 600 v i qbs quiescent v bs supply current 45 70 a i qcc quiescent v cc supply current 4 6 ma v in = 0 v or 5 v v in = 0 v or 5 v i in+ logic 1 input bias current (out = hi) 150 200 v in = 0 v i in- logic 0 input bias current (out = lo) 110 150 v in = 5 v i sd+ high shutdown bias current 5 10 a sd = 5 v i sd- low shutdown bias current 100 na sd = 0 v i itrip+ high itrip bias current 5 10 a itrip = 5 v i itrip- low itrip bias current 100 na itrip = 0 v i fltclr+ high fault clear input bias current 150 200 flt-clr = 0 v i fltclr- low fault clear input bias current 110 150 a flt-clr = 5 v irs2133d 7.6 8.6 9.6 v bsuv+ v bs supply undervoltage positive going threshold irs2135d 9.2 10.4 11.6 irs2133d 7.2 8.2 9.2 v bsuv- v bs supply undervoltage negative going threshold irs2135d 8.3 9.4 10.5 irs2133d 0.4 v bsuvh v bs supply undervoltage lockout hysteresis irs2135d 1 irs2133d 7.6 8.6 9.6 v ccuv+ v cc supply undervoltage positive going threshold irs2135d 9.2 10.4 11.6 irs2133d 7.2 8.2 9.2 v ccuv- v cc supply undervoltage negative going threshold irs2135d 8.3 9.4 10.5 irs2133d 0.4 v ccuvh v cc supply undervoltage lockout hysteresis irs2135d 1 v r on, flt fault low on-resistance 55 75 ? i o+ output high short circuit pulsed current 200 250 v out = 0 v, v in = 0 v pw 10 s i o- output low short circuit pulsed current 420 500 ma v out = 15 v, v in = 5 v pw 10 s prelim i nary downloaded from: http:///
www.irf.com 4 irs2133d/irs2135d(j&s)pbf static electrical charact eristics C (continued) v bias (v cc , v bs1,2,3 ) = 15 v, unless otherwise specified and t a = 25 c. all static parameters other than i o and v o are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the respective output leads: ho1, 2,3 or lo1,2,3. symbol definition min. typ. max. units test conditions r bs integrated bootstrap diode resistance 200 ? v os amplifier input offset voltage 10 mv ca+ = 0.2 v, ca- = cao i in,amp amplifier input bias current 50 na ca+ = ca- = 2.5 v cmrr amplifier common mode rejection ratio tbd 80 ca+ = 0.1 v & 5 v, ca- = cao psrr amplifier power supply rejection ratio tbd 75 db ca+ = 0.2 v, ca- = cao, v cc = 10 v & 20 v v oh,amp operational amplifier high leve l output voltage 4.9 5.2 5.4 v ca+ = 1 v, ca- = 0 v v ol,amp operational amplifier low leve l output voltage 30 mv ca+ = 0 v, ca- = 1 v i src,amp operational amplifier out put source current 4 7 ca+ = 1 v, ca- = 0 v, cao = 4 v i snk,amp operational amplifier out put sink current 1 2.1 ca+ = 0 v, ca- = 1 v, cao = 2 v i o+,amp operational amplifier output high short circuit current 10 ca+ = 5 v, ca- = 0 v, cao = 0 v i o-,amp operational amplifier output low short circuit current 4 ma ca+ = 0 v, ca- = 5 v, cao = 5 v note 1: please refer to feature description section fo r integrated bootstrap f unctionality information. dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v s1,2,3 = v ss , t a = 25 c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t on turn-on propagation delay 400 500 700 t off turn-off propagation delay 400 500 700 t r turn-on rise time 80 125 t f turn-off fall time 35 55 v in = 0 v & 5 v v s1,2,3 = 0 v to 600 v t sd sd to output shutdown propagation delay 400 550 750 t itrip itrip to output shutdown propagation delay 400 660 920 t bl itrip blanking time 400 t flt itrip to fault propagation delay 350 550 870 t flt, in input filter time ( hin, lin, and sd) 325 t fltclr flt-clr to fault clear time 600 850 1100 dt deadtime, ls turn-o ff to hs turn-on & hs turn-off to ls turn-on 150 230 350 ns sr+ operational amplifier slew rate (+) 5 10 sr- operational amplifier slew rate (-) 2.4 3.2 v/s 1 v step input note 2: for high side pwm, hin pulse width must be > 1 s. prelim i nary downloaded from: http:///
www.irf.com 5 irs2133d/irs2135d(j&s)pbf fig. 1. input/output timing diagram fig. 2. deadtime waveform definitions fig. 3. input/output switching time waveform definitions prelim i nary downloaded from: http:///
www.irf.com 6 irs2133d/irs2135d(j&s)pbf fig. 4. overcurrent shutdown switching time waveform definitions fig. 5. input filter function fig. 6. diagnostic feedback operational amplifier circuit prelim i nary downloaded from: http:///
www.irf.com 7 irs2133d/irs2135d(j&s)pbf lead definitions symbol description hin1,2,3 logic input for high side gate driver outputs (ho1,2,3), out of phase lin1,2,3 logic input for low side gate driver outputs (lo1,2,3), out of phase fault indicates over-current or undervoltage lock out (low side) has occurred, negative logic v cc logic and low side fixed supply itrip input for over-current shut down flt-clr logic input for fault clear, negative logic sd logic input for shut down cao output of current amplifier ca- negative input of current amplifier ca+ positive input of current amplifier v ss logic ground com low side return v b1,2,3 high side floating supplies ho1,2,3 high side ga te drive outputs v s1,2,3 high side floating supply returns lo1,2,3 low side gate drive outputs lead assignments prelim i nary downloaded from: http:///
www.irf.com 8 irs2133d/irs2135d(j&s)pbf functional block diagram prelim i nary downloaded from: http:///
www.irf.com 9 irs2133d/irs2135d(j&s)pbf 1 features description 1.1 integrated bootstrap functionality the irs213(3,5)d family embeds an integrated bootstrap fet that allows an alternative drive of the bootstrap supply for a wide range of applications. there is one bootstrap fet for each channel and it is connected between each of the floating supply (v b1 , v b2 , v b3 ) and v cc (see fig. 7). the bootstrap fet of each c hannel follows the state of the respective low side output stage (i.e., bootfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 1.1(v cc ). in that case the bootstrap fet stays off until the v b voltage returns below that threshold (see fig. 8). fig. 7. simplified bootfet connection vcc=15v vth~17v lo bootfet on bootfet off bootfet on bootstrap fet state phase voltage fig. 8. state diagram the bootstrap fet is suitable for most pwm modulation schemes and can be used either in parallel with the external bootstrap network (diode+resistor) or as a replacement of it. the use of the integrated boot strap as a replacement of the external bootstrap network may have some limitations in the following situations: - when used in non-complementary pwm schemes (typically 6-step modulations) - at a very high pwm duty cycle due to the bootstrap fet equivalent resistance (r bs , see page 4). in these cases, better performances can be achieved by using the irs213(3,5) non d version with an external bootstrap network. 2 pcb layout tips 2.1 distance from h to l voltage the irs213(3,5)j package lacks some pins (see page 6) in order to maximizing the distance between the high voltage and low voltage pins. its strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (v b1,2,3 , v s1,2,3 ) side. 2.2 ground plane to minimize noise coupling the ground plane must not be placed under or near the high voltage floating side. 2.3 gate drive loops current loops behave like an antenna, which are able to receive and transmit em noise (see fig. 9). in order to reduce em coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. fig. 9. antenna loops 2.4 supply capacitors supply capacitors must be placed as close as possible to the device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/resistance. prelim i nary downloaded from: http:///
www.irf.com 10 irs2133d/irs2135d(j&s)pbf 2.5 routing and placement power stage pcb parasitic may generate dangerous voltage transients for the gate driver and the control logic. in particular its recommended to limit phase voltage negative transients. in order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray in ductance. see dt04-4 at www.irf.com for more detai led information. prelim i nary downloaded from: http:///
www.irf.com 11 irs2133d/irs2135d(j&s)pbf figures 10-40 provide information on the experimental performance of the irs2133ds hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples from multiple wafer lots were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data po int at each of the tested te mperatures) that have been connected together to illustrate the understood trend. the individual data points on the curve were determined by calculating the averaged experim ental value of the parameter (for a given temperature). 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) exp . fig. 10. turn-on propagati on delay vs. temperature fig. 11. turn-off propagati on delay vs. temperature fig. 12. turn-on rise time vs. temperature fig. 13. turn-off fall time vs. temperature 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns ) exp . 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) exp . 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) exp . prelim i nary downloaded from: http:///
www.irf.com 12 irs2133d/irs2135d(j&s)pbf fig. 14. dt propagation delay vs . temperature fig. 15. t itrip propagation delay vs. temperature fig. 16. itrip to fault propagation delay vs. temperature fig. 17. fault low on resistance vs. temperature fig. 18. v cc quiescent current vs. temperature fig. 19. v bs quiescent current vs. temperature 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip to fault propagation delay (ns) exp. 300 600 900 1200 1500 1800 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip propagation delay (ns ) exp . 0 40 80 120 160 200 -50 -25 0 25 50 75 100 125 temperature ( o c) fault low on resistance ( ohm) exp . 0 4 8 12 16 20 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc quiescent current (ma) exp . 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs quiescent supply current (ua) exp . 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) dt propagation delay (ns) exp . prelim i nary downloaded from: http:///
www.irf.com 13 irs2133d/irs2135d(j&s)pbf fig. 20. v ccuv+ threshold vs. temperature fig. 21. v ccuv- threshold vs. temperature fig. 22. v bsuv+ threshold vs. temperature fig. 23. v bsuv- threshold vs. temperature fig. 24. itrip positive goi ng threshold vs. temperature fig. 25. itrip negative going threshold vs. temperature 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) exp . 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv- threshold (v) exp . 6 7 8 9 10 11 12 - 5 0- 2 5 0 2 55 07 51 0 01 2 5 temperature ( o c) v bsuv+ threshold (v) exp . 6 7 8 9 10 11 12 - 5 0- 2 5 0 2 55 07 51 0 01 2 5 temperature ( o c) v bsuv- threshold (v) exp . 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip positive going threshold (mv) ex p. 100 300 500 700 900 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip negative going threshold (mv) exp . prelim i nary downloaded from: http:///
www.irf.com 14 irs2133d/irs2135d(j&s)pbf fig. 26. output high sc pu lsed current vs. temperature fig. 27. output low sc puls ed current vs. temperature fig. 28. "high" itrip bi as current vs. temperature 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) "low" itrip bias current (na) exp . fig. 29. "low" itrip bias current vs. temperature 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) v oh,amp (v) exp . 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) v ol,amp (mv) exp . fig. 30. v oh,amp vs. temperature fig. 31. v ol,amp vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) output high sc pulsed current (ma) exp . 0 150 300 450 600 750 -50 -25 0 25 50 75 100 125 temperature ( o c) output low sc pulsed current (ma) exp . 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) "high" itrip input bias current (ua) exp. prelim i nary downloaded from: http:///
www.irf.com 15 irs2133d/irs2135d(j&s)pbf fig. 32. sr+,amp vs. temperature fig. 33. sr-,amp vs. temperature fig. 34. i snk,amp vs. temperature fig. 35. i src,amp vs. temperature fig. 36. i o-,amp vs. temperature fig. 37. i o+,amp vs. temperature 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature ( o c) sr+,amp (v/us) exp . 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) sr-,amp (v/us) exp . 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) i snk,amp (ma) exp . 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 temperature ( o c) i src,amp (ma) exp. 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) i o-,amp (ma) exp . 0 4 8 12 16 20 -50 -25 0 25 50 75 100 125 temperature ( o c) i o+,amp (ma) exp. prelim i nary downloaded from: http:///
www.irf.com 16 irs2133d/irs2135d(j&s)pbf fig. 38. v os,amp vs. temperature fig. 39. psrr vs. temperature fig. 40. cmrr vs. temperature 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 temperature ( o c) psrr (db) exp. -10 10 30 50 70 90 -50 -25 0 25 50 75 100 125 temperature ( o c) vo s,amp (mv) exp . 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 temperature ( o c) cmrr (db) exp . prelim i nary downloaded from: http:///
www.irf.com 17 irs2133d/irs2135d(j&s)pbf case outlines prelim i nary downloaded from: http:///
www.irf.com 18 irs2133d/irs2135d(j&s)pbf case outlines prelim i nary downloaded from: http:///
www.irf.com 19 irs2133d/irs2135d(j&s)pbf carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c prelim i nary downloaded from: http:///
www.irf.com 20 irs2133d/irs2135d(j&s)pbf carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c prelim i nary downloaded from: http:///
www.irf.com 21 irs2133d/irs2135d(j&s)pbf worldwide headquarters: 233 kansas street, el segundo, ca 90245 tel (310) 252-7105 this part has been qua lified per industrial level http://www.irf.com data and specificati ons subject to change without notice. 5/19/2006 order information 28-lead pdip irs2133dpbf 28-lead pdip irs2135dpbf 28-lead soic irs2133dspbf 28-lead soic irs2135dspbf 44-lead plcc irs2133djpbf 44-lead plcc IRS2135DJPBF 28-lead soic tape & reel irs2133dstrpbf 28-lead soic tape & reel irs2135dstrpbf 44-lead plcc tape & reel irs2133djtrpbf 44-lead plcc tape & reel irs2135djtrpbf prelim i nary downloaded from: http:///

▲Up To Search▲

Price & Availability of IRS2135DJPBF

	To Download IRS2135DJPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .